The fabrication of integrated circuits in silicon substrates may require the assembly of two silicon wafers. For example, three-dimensional structures comprise components fabricated on at least two separate wafers that are then assembled.
Mention will also be made of backlit imaging devices in which the photodetection cells are placed near the back side of the substrates in which they are fabricated. These substrates are generally thinned in mechanical polishing or grinding steps to bring the back surface of the active regions of the photodetection cells closer. To enable this thinning, a second wafer of silicon is attached to the front side of the first substrate to form a handle.
Moreover, during fabrication of three-dimensional structures, vertical through-interconnections, called TSVs (through-silicon vias), are produced through at least one silicon wafer. Generally, this silicon wafer is thinned in a mechanical polishing or grinding step to enable production of short through-silicon vias.
A conventional assembly of two wafers, for example, silicon wafers, is illustrated in FIG. 1a. In this figure, two silicon wafers P1 and P2 are schematically illustrated. To bond the two wafers, a bonding layer OX, for example, a layer of silicon dioxide (SiO2), is formed on the surface of the two wafers. This may be performed, for example, in a growth step or by depositing silicon dioxide (SiO2).
The two wafers P1 and P2 are generally wafers that are 200 mm or 300 mm in diameter, and they conventionally comprise a bevelled peripheral part BIS. The bevelled peripheral part BIS may extend over a portion of the wafers P1 and P2, which is about 1 mm to 3 mm in width.
After bonding, a cavity CV is formed between the bevelled peripheral parts BIS of the two wafers P1 and P2. The presence of the cavity CV has the particular drawback of not allowing the peripheral parts of the wafers to be rigidly connected to each other during bonding.
Thus, during the thinning of the wafer P1 (FIG. 1b), the edge of the wafer P1 is too fragile and may delaminate and cause the bevelled peripheral part BIS to crack. This cracking may produce splinters that can deeply scratch the surface of the wafer P1 during the thinning step, and thus represents a source of particulates.
Before bonding, it is possible to cut off the bevelled parts of the silicon wafer to be thinned (FIG. 2a) using a technique well know to those skilled in the art called edge grinding or edge trimming. In this figure, the bevelled peripheral part BIS of the wafer P1 has been trimmed, for example, mechanically trimmed, before the wafer P1 is thinned.
In FIG. 2b, the wafer P1 is shown after the thinning step. The absence of the bevelled peripheral part BIS makes it possible to obtain a thickness of about a micron without cracks appearing. Nonetheless, apart from the fact that an additional step is performed in the assembly of two wafers, the cutting may also create particles that contaminate equipment.